Day 0 (Mon 15.5. 12h): Opening section – Gordan Galić (Xylon) – Introduction to Xylon – 30 min - 1h

Introduction to Xylon.

Image processing in embedded applications.


Day 1 (Tue 16.5. 16h): prof.dr.sc. Mladen Vučić (FER) – VHDL and digital design – 3 – 4 hours

Introduction to VHDL.

Synchronous digital design.


Day 2 (Wed 17.5. 16h): Davor Petrinović (FER) – Image processing – scaling - 3 hours

Image scaling operations: nearest neighbour, bilinear interpolation, bicubic interpolation…

Arithmetic (integer, fixed point, floating point)


Day 3 (Thu 18.5. 16h): Gordan Galić, Jura Ivanović (Xylon) – Xilinx Zynq AP SoC and ZedBoard development platform from Avnet Electronic Marketing – 4 hours

Introduction to the hardware platform (Avnet ZedBoard Development Kit)

Introduction to the Xilinx Zynq System-on-Chip (SoC)

Short introduction into the student FPGA development challenge

Detail explanation of key embedded resources needed for successful project implementation, i.e. BRAM resources, registers implementation, etc.


Day 4 (Fri 19.5. 14h): Jura Ivanović, Marko Polović (Xylon) – Introduction to Vivado Design Suite and SDK – 2 hours

Installation tips and hints

Quick guide to Xilinx Vivado (FPGA part) and SDK (SW part) tools

Digital simulations in the Vivado tools


Xylon – Introduction to student FPGA development challange – 2 hours

Platform design provided by Xylon

Explanation of HW & SW interfaces for new functionality blocks